LEARNING FPGA

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the functionality after shipping, partial re-configuration of a portion of the design and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.

FPGA Basics

FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together"—somewhat like many (changeable) logic gates that can be inter-wired in (many) different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flopsor more complete blocks of memory.

Fig 1: What is FPGA is?

In addition to digital functions, some FPGAs have analog features. The most common analog feature is programmable slew rate and drive strength on each output pin, allowing the engineer to set slow rates on lightly loaded pins that would otherwise ring unacceptably, and to set stronger, faster rates on heavily loaded pins on high-speed channels that would otherwise run too slow. Another relatively common analog feature is differential comparators on input pins designed to be connected to differential signaling channels.

Fig 2: Basics Building Block of FPGA

A few "mixed signal FPGAs" have integrated peripheral analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) with analog signal conditioning blocks allowing them to operate as a system-on-a-chip. Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and field-programmable analog array (FPAA), which carries analog values on its internal programmable interconnect fabric.

Figure 3: An Altera Cyclone II FPGA

Historically, FPGAs have been slower, less energy efficient and generally achieved less functionality than their fixed ASIC counterparts. A study has shown that designs implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic power, and are three times slower than the corresponding ASIC implementations.

Integrated circuit costs are rising aggressively
ASIC complexity has lengthened development time
R&D resources and headcount are decreasing
Revenue losses for slow time-to-market are increasing
Financial constraints in a poor economy are driving low-cost technologies

Fig 4: Integrated Circuits

These trends make FPGAs a better alternative than ASICs for a larger number of higher-volume applications than they have been historically used for, to which the company attributes the growing number of FPGA design starts (see History).

Some FPGAs have the capability of partial re-configuration that lets one portion of the device be re-programmed while other portions continue running.

Complex Programmable Logic Devices (CPLD)

The primary differences between CPLDs (Complex Programmable Logic Devices) and FPGAs are architectural. A CPLD has a somewhat restrictive structure consisting of one or more programmable sum-of-products logic arrays feeding a relatively small number of clocked registers. The result of this is less flexibility, with the advantage of more predictable timing delays and a higher logic-to-interconnect ratio. The FPGA architectures, on the other hand, are dominated by interconnect. This makes them far more flexible (in terms of the range of designs that are practical for implementation within them) but also far more complex to design for.

In practice, the distinction between FPGAs and CPLDs is often one of size as FPGAs are usually much larger in terms of resources than CPLDs. Typically only FPGA's contain more advanced embedded functions such as adders, multipliers, memory, serdes and other hardened functions. Another common distinction is that CPLDs contain embedded flash to store their configuration while FPGAs usually, but not always, require an external flash.

Fig 5: What is CPLD?

FPGA or DSP (Make a Choice)

The DSP is a specialised microprocessor - typically programmed in C, perhaps with assembly code for performance. It is well suited to extremely complex maths-intensive tasks, with conditional processing. It is limited in performance by the clock rate, and the number of useful operations it can do per clock. As an example, a TMS320C6201 has two multipliers and a 200MHz clock – so can achieve 400M multiplies per second.

In contrast, an FPGA is an uncommitted "sea of gates". The device is programmed by connecting the gates together to form multipliers, registers, adders and so forth. Using the Xilinx Core Generator this can be done at a block-diagram level. Many blocks can be very high level – ranging from a single gate to an FIR or FFT. Their performance is limited by the number of gates they have and the clock rate. Recent FPGAs have included Multipliers especially for performing DSP tasks more efficiently. – For example, a 1M-gate Virtex-II™ device has 40 multipliers that can operate at more than 100MHz. In comparison with the DSP this gives 4000M multiplies per second.

DSP vs FPGA

Why do we need FPGAs ?

By the early 1980’s Large scale integrated circuits (LSI) formed the back bone of most of the logic circuits in major systems. Microprocessors, bus/IO controllers, system timers etc were implemented using integrated circuit fabrication technology. Random “glue logic” or interconnects were still required to help connect the large integrated circuits in order to :

generate global control signals (for resets etc.)
data signals from one subsystem to another sub system.

Systems typically consisted of few large scale integrated components and large number of SSI (small scale integrated circuit) and MSI (medium scale integrated circuit) components.

Intial attempt to solve this problem led to development of Custom ICs which were to replace the large amount of interconnect. This reduced system complexity and manufacturing cost, and improved performance.However, custom ICs have their own disadvantages. They are relatively very expensive to develop, and delay introduced for product to market (time to market) because of increased design time. There are two kinds of costs involved in development of Custom ICs:

1. cost of development and design
2. cost of manufacture

( A tradeoff usually exists between the two costs)

WHY FPGA? 5 REASONS FOR FPGA PROCESSOR

Therefore the custom IC approach was only viable for products with very high volume, and which were not time to market sensitive.

FPGAs were introduced as an alternative to custom ICs for implementing entire system on one chip and to provide flexibility of reporogramability to the user. Introduction of FPGAs resulted in improvement of density relative to discrete SSI/MSI components (within around 10x of custom ICs). Another advantage of FPGAs over CustomICs is that with the help of computer aided design (CAD) tools circuits could be implemented in a short amount of time (no physical layout process, no mask making, no IC manufacturing)
test

Fig 6: FPGA comparative analysis

Altera has created a number of FPGAs having different specs depend upon there use. These are given below:

Advance and High Cost FPGAs

	Highest bandwidth, highest integration 28-nm FPGAs with ultimate flexibility New class of application-targeted devices with integrated 28-Gbps and backplane-capable 12.5-Gbps transceivers, integrated hard intellectual property (IP) blocks including Embedded HardCopy^® Blocks, and user-friendly partial reconfiguration 30% lower total power compared to Stratix^® IV FPGAs Low-risk, low-cost path to HardCopy ASICs for higher volume production

	Highest performance, highest density, and lowest power 40-nm FPGAs Best-in-class 11.3-Gbps transceivers and high-performance memory interfaces deliver unprecedented system bandwidth with superior signal integrity

	The industry's lowest power, high-performance 65-nm FPGAs Logic rich (L), enhanced for digital signal processing (DSP) and memory (E), and transceiver (GX) variants Targets high-end core system processing designs, supported by industry-leading FPGA design tools, and provides a risk-free path to HardCopy ASICs

	High-performance 90-nm FPGA family Includes best-in-class 6.375-Gbps transceiver (GX) variant Advanced FPGA architecture, high-performance adaptive logic module (ALM) with 8-input fracturable look-up table (LUT), large on-chip memory, embedded DSP blocks, high-speed external interface support, and risk-free path to HardCopy ASICs

	First generation in the Stratix FPGA family Embedded DSP blocks, on-chip memory, flexible I/Os Broad range of IP support including Nios^® II processors

Mid-Range FPGAs

	28-nm FPGAs that balance cost and power with performance Four variants offer low-power 6.375 -Gbps and 10.3125 -Gbps transceivers with an optional dual-core ARM Cortex-A9 hard processor system Delivers up to 40 percent lower total power vs. 6.375-Gbps Arria II FPGAs High level of integration with abundant hard IP blocks

	Cost-optimized 40-nm FPGAs with transceivers Offers lowest total power for transceiver-based applications Includes 6.375-G transceivers, rich DSP and RAM resources, and more performance than other devices in its class

	Arria^® GX 90-nm FPGAs with transceivers Optimized for 3-Gbps serial I/O applications Simple solution for bridging and end-point applications

Lowest Cost and Power FPGAs


	28-nm FPGAs providing industry’s lowest system cost and power Six variants offer mix of logic, 3.125-Gbps or 5-Gbps transceivers, and single- or dual-core ARM Cortex-A9 hard processor system Delivers up to 40 percent lower total power and up to 30 percent lower static power vs. the previous generation High level of integration with abundant hard IP blocks

	Fourth generation in the Cyclone^® series of lowest cost, lowest power FPGAs Two variants: Cyclone IV GX FPGAs with integrated 3.125-Gbps transceivers and Cyclone IV E FPGAs Broad range of IP support including Nios II embedded processor support

	Third generation in the Cyclone series of lowest cost FPGAs Unprecedented combination of power, functionality, and cost Broad range of IP support including Nios II embedded processor support

	Second generation in the lowest cost FPGA series Embedded 18x18 DSP multipliers, on-chip memory, and mid-range speed I/Os Broad range of IP support, including Nios II embedded processor support

	First generation in the lowest cost FPGA series, where cost is paramount On-chip memory, lower density applications, low to moderate speed I/Os Broad range of IP support including Nios II embedded processor support